A programmable device (e.g., PSoC, FPGA, etc.) performs a configuration by reading configuration data from a program memory (e.g., read only memory or flash memory) and copying the configuration data to state registers (e.g., configuration registers) of the programmable device. Functional blocks (e.g., which perform user-defined logic functions), I/O blocks (e.g., which configure input/output blocks interfacing to external devices), and/or signal routing resources (e.g., which connect the functional blocks to the I/O blocks), for example, may be established this way.
A central processing unit (CPU) and/or a controller of the programmable device may be used to perform the configuration during the reset and/or runtime. Using the CPU for the configuration may be undesirable because the CPU is inefficient and therefore slow (e.g., taking longer clock cycles) in performing the configuration which involves moving the configuration data from the program memory to the configuration registers.
This latency causes longer delays to achieve a runtime operation from a reset state. Additionally, the configuration process may be visible to the user of the programmable device because the configuration is taking place in foreground by the processor rather than in background.